The present invention generally relates to mass storage devices for use with computers and other processing apparatuses. More particularly, this invention relates to a high speed non-volatile (permanent memory-based) mass storage device that utilizes flash memory components and on-board means for performing thermal treatments capable of increasing the endurance of the memory components.
Mass storage devices such as advanced technology (ATA) or small computer system interface (SCSI) drives are rapidly adopting non-volatile memory technology, such as flash memory components (chips) or another emerging solid-state memory technology, including phase change memory (PCM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), ferromagnetic random access memory (FRAM), organic memories, or nanotechnology-based storage media such as carbon nanofiber/nanotube-based substrates. Currently the most common solid-state technology uses NAND flash memory components as inexpensive storage memory, often in a form commonly referred to as a solid-state drive (SSD).
NAND flash memory has several limitations that are inherent to the design and function of the technology. Briefly, flash memory components store information in an array of floating-gate transistors, referred to as cells. The cell of a NAND flash memory component has a top gate (TG) and a floating gate (FG), the latter being sandwiched between the top gate and the channel of the cell. The floating gate is separated from the channel by a layer of tunnel oxide. Data are stored in a NAND flash cell in the form of a charge on the floating gate which, in turn, defines the channel properties of the NAND flash cell by either augmenting or opposing the charge of the top gate. The process of programming a NAND cell requires injection of electrons into the floating gate by quantum mechanical tunneling. Programming and erasing of NAND flash cells is an extremely harsh process utilizing electrical fields in excess of 10 million V/cm to move electrons through the tunnel oxide layer.
The brute force approach used to program and erase NAND flash results in wear and fatigue of the cells by causing atomic bond sites in the tunnel oxide layer to break. The broken-bond sites then become a trap for electrons that mimic charges in the floating gate, which can cause false data to be read from the NAND flash cells or prevent correct erasing of the cells. In the case of single level cells, where only one bit is stored per cell, the trapping of electrons is a relatively minor issue that gradually increases to a critical threshold over tens of thousands of program and erase cycles. However, in the case of multilevel cells that use, for example, four different levels to encode two bits per cell, the “drift” in charge caused by a steady build-up of electrons in the tunnel oxide layer and at the borders between the layers constitutes the predominant limitation of write endurance. In 55 nm process technology, typical write endurance is on the order of about 10,000 program/erase cycles per cell, but with smaller process technologies, this number dramatically declines. For example, for a 3× nm process, typical write endurance is on the order of about 3000 to 5000 cycles per cell, and for a 22 nm process write endurance estimates decrease toward about 900 to about 1200 program/erase cycles per cell.
The build-up of charge in the oxide layer and its boundaries also depends on the time allowed between program/erase cycles of cells. That is, over time the tunnel oxide layer releases trapped electrons. This process is referred to as detrapping of electrons, and is sometimes also described as self-healing of the tunnel oxide. It is also known in the art that, above about 75° C., possible reconditioning may occur with the tunnel oxide layer that may skew the results of write endurance tests performed on NAND flash-based SSD. In particular, a detrimental side effect of heat is reduced data retention, in that heat also increases leakage current from the floating gate, thereby altering the charge and, by extension, the program state of a NAND flash cell.
Hierarchical storage management (HSM) is a data storage technique that moves data between relatively high-cost “first tier” storage media and other less expensive but slower storage media. Traditionally, HSM systems have utilized high-speed storage devices such as rotational media-based hard disk drives (HDD) as the first tier of storage media, and optical discs, magnetic tape drives and/or other less expensive but slower storage media as higher tiers of the HSM system. Recently, this landscape has changed in that the cost of HDDs has decreased considerably and, simultaneously, SSDs have gained substantial market share. Compared to hard disk drives, flash-based SSDs are extremely fast, especially with respect to access times since no rotational or seek latencies are incurred at initial data accesses. Consequently, SSDs have become a viable candidate for the first tier storage media in HSM systems. However, in this particular role data are constantly rewritten, causing excessive wear because of very high erase/program cycle frequencies.
In view of the above, it would be desirable to speed up self-healing and thereby increase the write endurance of solid-state memory components of a mass storage device, for example, a solid-state drive used as a first tier storage media in a HSM system.